01
industry
Automotive & functional safety
ISO 26262-grade RTL, AUTOSAR BSW, and verification flows for tier-1 suppliers and automotive start-ups.
asic · soc · embedded linux · security
Production-grade silicon. Secure embedded platforms.
A senior team covering the full chain from RTL sign-off through Yocto BSP through Common Criteria evaluation. Principal-only delivery — no junior hand-offs.
// covering
asic · soc · dsp · wireless phy · yocto bsp · cc / fips
// f₁
// f₁ + f₂ · FIR filtered
Why work with SiERA
// senior team
Principal-only delivery. Every engagement is run by an engineer with deep domain experience — no juniors to hand your project to.
// brainport
Based in the Netherlands — Eindhoven and Den Bosch — at the heart of Europe’s densest hardware cluster.
// silicon to cert
RTL sign-off, SoC architecture, Yocto BSP, and Common Criteria / FIPS 140-3 evaluation under one roof.
// open record
Granted patents, peer-reviewed publications at DAC/DATE/EMSOFT, IEEE Senior membership, IEEE/IETF standards contributions, and upstream open-source cores.
Three services. End to end.
A complete digital design flow you actually own, senior design on the blocks that matter, and defense-grade embedded platforms carried through Common Criteria or FIPS evaluation.
// service · 01
Digital design flow setup
Install a complete, reproducible digital design flow — design entry through sign-off — on commercial EDA or open-source tooling. Your team owns it on day one.
Makefile
// example
$ make lint
$ make sim # verilator regression
$ make cov # 100% line, 96% branch
$ make synth # yosys → openroad
Learn more
→
// service · 02
Silicon design — ASIC, DSP & SoC architecture
Take architecture, RTL, or microarchitecture and rework it against measurable targets — area, throughput, power, latency. Ship it back as soft IP with a self-checking testbench and a clean synthesis report.
−42% area
2.1× throughput
−31% power
Learn more
→
// service · 03
Secure embedded platforms & certification
Take a Linux-based platform from BSP through certification — Yocto, secure boot, OP-TEE, full-disk encryption, post-quantum crypto — and deliver the Security Target and assurance evidence a Common Criteria or FIPS evaluator expects.
CC / NIAP security target
FIPS 140-3 validated crypto
STIG hardening
PQC Kyber / ML-KEM
Learn more
→
A short, transparent loop.
The same three phases on every engagement. Predictable for both sides — and easy for your team to plug into.
01 / scope
Scope
Architecture, requirements, risks. A short, written agreement before any RTL or BSP gets touched.
// you keep written spec · risk register · Makefile skeleton
02 / build
Build
RTL, self-checking testbench, BSP, or Security Target — lint clean, reproducible, auditable. Iteration cycles you can watch.
// you keep RTL · testbench · BSP · coverage · synth log
03 / hand-off
Hand-off
Soft IP, or a Yocto image, or a CC evidence pack — plus a one-page architecture note, a Makefile, and a README. Built for the next engineer.
// you keep soft IP · arch note · Makefile · README · evaluation pack
Trusted across automotive, telecom, and consumer silicon.
Engagements span the silicon stack — from automotive functional-safety work to consumer DSP front-ends.
02
industry
Wireless & telecom
BLE, Bluetooth classic, 802.15.4, and UHF RFID PHY — demodulator architecture, FEC, and filter IP.
03
industry
Defense-grade embedded
Common Criteria / NdCPP, FIPS 140-3, STIG-aligned platforms with post-quantum-ready cryptography.
// named references available under nda
Receipts, not adjectives.
Public record across academia, certification, open-source, and standards bodies — class-level here, with named references available under NDA.
// EU research university PhD-level electrical engineering Doctoral research in digital signal processing & integrated circuits
// EU research university PhD-level computer science Doctoral research in hard real-time scheduling & system-level design
// EU research university PhD-level electronics & communications Doctoral research in wireless PHY and RFID receiver algorithms
// exida ISO 26262 Functional Safety Practitioner Automotive functional safety — FSP certified
// Institute of Electrical and Electronics Engineers IEEE Senior Member Elevated grade — awarded for significant contributions to the field
// GNU Octave community Open-source package maintainer Maintainer of an official fixed-point arithmetic package for signal-processing modelling
// Accellera Systems Initiative Accellera SystemC contributor Upstream contributions to the SystemC reference implementation
// European network on HPC & embedded architecture HiPEAC Paper Award Peer-reviewed award for research published at DAC
// DSP, processor, and filter building blocks Open IP core contributor Synthesisable open cores released to the silicon community
Engagement
Have a block, a BSP, or a Security Target that needs to ship?
Discovery sprints from one week. Project engagements from a month. We respond within one business day.