01 fixed fee
Discovery sprint
from €4,000 1 – 2 weeks
Scoping, architecture review, risk audit. You leave with a written plan you can hand to any team — us, your in-house engineers, or another contractor.
DiscussThree ways we work with hardware teams.
Set up your digital design flow, take a stubborn block or full SoC all the way to sign-off, or carry an embedded platform through Common Criteria and FIPS evaluation. You keep everything we build — flow, RTL, BSP, Security Target, and the documentation that lets your team carry it forward.
Digital design flow setup
Most teams bleed weeks bolting together a flow before the first line of RTL. We install a complete, reproducible flow — design entry through sign-off — using your preferred EDA stack or a fully open-source toolchain. Your team owns it on day one.
// deliverables
- Design entry templates (SystemVerilog, SystemC, or Verilog)
- Linting & static checks (Verilator, SpyGlass, or equivalent)
- Self-checking testbench harness with reproducible regressions
- Coverage closure plan and reports (functional + code)
- Synthesis flow + STA constraints (open source or commercial)
- Reusable Makefiles and CI hooks for daily regressions
// toolchain — your call
Commercial
- Synopsys VCS / DC
- Cadence Xcelium / Genus
- Mentor Questa
- Synopsys SpyGlass
- JasperGold
Open source
- Verilator
- Yosys + nextpnr
- OpenROAD
- SymbiYosys
- GTKWave
Makefile — daily regression
// example
SIM ?= verilator
TOP ?= fir_lowpass
TB_TOP ?= tb_$(TOP)
regress: lint $(SIM) coverage report
lint:
verilator --lint-only -sv $(RTL_FILES)
verilator:
verilator --cc --trace --exe $(RTL_FILES) tb/$(TB_TOP).cpp
$(MAKE) -C obj_dir -f V$(TOP).mk V$(TOP)
./obj_dir/V$(TOP)
coverage:
verilator_coverage --annotate logs/annotate logs/coverage.dat
// the flow
Eight stages — every one repeatable.
From initial spec through tape-out hand-off. Every stage produces an artefact you keep, in your own repo, runnable by your team.
01
Specrequirements
02
Architectureblock diagram
03
µArchpipeline plan
04
RTLverilog / sv
05
DVself-checking
06
Synthgate netlist
07
STAtiming close
08
Sign-offgds / handoff
01 / 08
Silicon design — ASIC, DSP & SoC architecture
Block, subsystem, or full SoC. We take architecture, RTL, or microarchitecture and rework it against measurable targets — area, throughput, power, latency — and ship it back as soft IP with a self-checking testbench and a clean synthesis report. Wireless PHY (BLE, BT, 802.15.4, RFID), DSP (fixed-point filters, FEC, equalizers), NPU and matrix accelerators, bus and interconnect architecture all live here.
// deliverables
- Microarchitecture review and optimisation plan
- RTL design or refactor with bit-true / cycle-true reference model
- Fixed-point analysis & Matlab/Octave golden model
- Virtual prototype / SystemC performance model for early SW bring-up
- Verification suite that passes on commercial and open simulators
- Synthesis & timing reports against your PDK
- Documentation pack ready for hand-off to your team
// common targets
Area gate count, register footprint
Throughput Msamples/s, MAC throughput
Power switching, leakage, clock-gating coverage
Latency pipeline depth, critical path
Secure embedded platforms & certification
Take a Linux-based embedded platform from BSP through certification — Yocto, secure boot, OP-TEE, full-disk encryption, authenticated OTA, post-quantum crypto — and deliver the Security Target and assurance evidence a Common Criteria or FIPS evaluator expects to see. We have authored Security Targets against NdCPP, integrated FIPS-validated stacks into Yocto, and migrated production WPA3 links to Kyber.
// deliverables
- Yocto/Buildroot BSP with signed, reproducible images
- Secure-boot chain with measured boot and TPM attestation
- OP-TEE integration for key storage and tamper detection
- FIPS 140-3 cryptographic stack (TLS 1.2/1.3, SSH, MACsec, X.509 RFC 5280 / 8603)
- Post-quantum migration (Kyber / ML-KEM via OpenSSL + liboqs)
- Common Criteria Security Target authoring + evaluation support
- STIG-aligned kernel hardening, audit logging, CRL/OCSP revocation
// standards we work against
CC / NIAP Security Target, TOE design, evaluator interface
FIPS 140-3 validated cipher suites, CorSSL-in-Yocto
STIG kernel hardening, W^X, structured audit
RFC 5280 / 8603 X.509 chains, CNSA cipher suites
What we bring on day one.
A grouped view of the languages, methodology, and tooling we use across every engagement.
Languages How we describe hardware and the systems around it.
- SystemVerilog (SV)
- Verilog
- VHDL
- SystemC (SC)
- Matlab / Octave
- Python
- C / C++
- Bash
- Tcl
Methodology The discipline we bring to RTL and BSP on day one.
- RTL design
- SoC architecture
- Bit-true (BT) modelling
- Cycle-true (CT) modelling
- Fixed-point analysis
- Virtual prototyping
- Reproducible flows · Makefiles
Verification How we prove the design works before silicon — and after.
- Self-checking testbenches
- Digital verification (DV)
- SystemVerilog Assertions (SVA)
- Formal verification
- Coverage closure
- Sign-off
- Hybrid RTL/SystemC DV
Embedded & security From BSP through cryptographic stack through evaluation.
- Yocto · Buildroot
- Linux kernel & BSP
- OP-TEE · TPM · HSM
- Secure boot · FDE
- OpenSSL + liboqs (PQC)
- FIPS 140-3 · Common Criteria · STIG
Domains Where we have shipped at production scale.
- ASIC
- FPGA
- DSP
- SoC
- Wireless PHY (BLE · BT · 802.15.4 · RFID)
- NPU / AI acceleration
- Automotive (ISO 26262)
- Defense-grade embedded
Pick the shape that fits.
Three engagement shapes. Each one priced predictably so you can plan around it.
02 milestone-based
Project engagement
from €15,000 4 – 16 weeks
A scoped block, subsystem, or BSP delivered with RTL or Yocto image, testbench or evaluation pack, docs, lint/hardening clean, and synthesis or cert-ready reports. Weekly check-ins, code in your repo from day one.
Discuss 03 monthly retainer
Fractional senior
from €3,000 / mo ongoing
A few days a month embedded with your team — code reviews, mentoring, sign-off support, ISO 26262 or Common Criteria questions. For when you need senior bandwidth without a hire.
DiscussCommon questions.
Anything not covered here? Send a brief at /contact.
Do you sign NDAs?
Yes. Mutual NDAs before sharing any design specifics, and project work is covered by a written agreement that assigns IP ownership to the client.
Who owns the IP?
You do. All RTL, testbenches, BSPs, Security Targets, scripts, and documentation produced under a project engagement are work-for-hire and fully assigned to the client.
Can you work on-site?
Yes — short on-site stays for kick-off, integration, or sign-off support. The bulk of the work is remote unless your tooling or security boundary requires otherwise.
What if we have no EDA licences?
That’s the point of the open-source flow option. Verilator, Yosys, OpenROAD, and SymbiYosys cover most digital flows for early-stage designs. We can switch to commercial tools later without rewriting RTL.
Do you have foundry experience?
Yes — designs taped out to multiple processes, both with commercial PDKs and on open shuttle programmes (e.g. SkyWater 130nm).
Can you take a platform through Common Criteria or FIPS evaluation?
Yes. We have authored Security Target documents against NdCPP, interfaced directly with external CC evaluation bodies, and integrated FIPS 140-3 validated cryptographic libraries (including CorSSL) into Yocto images. STIG-aligned hardening, structured audit logging, and CRL/OCSP revocation chains are part of the standard deliverable.
Do you handle post-quantum crypto migration?
Yes. We have integrated Kyber (ML-KEM, FIPS 203) into wpa_supplicant/hostapd via OpenSSL + liboqs to replace ECDH in production WPA3 links. We can plan and execute a migration of your TLS, SSH, or link-layer key exchange onto the NIST PQC suite.
How do you charge?
Fixed fee for discovery sprints. Milestone-based for project engagements. Monthly retainer for fractional work. No hourly billing — predictable for both sides.
Engagement
Have a block, a BSP, or a Security Target that needs to ship?
Discovery sprints from one week. Project engagements from a month. We respond within one business day.