A senior boutique.
Principal-only delivery. Based in the Netherlands — Eindhoven and Den Bosch — at the heart of Europe’s densest hardware cluster. No founder, no hierarchy, no junior hand-offs.
Flat by design.
No founder, no hierarchy, no junior hand-offs.
SiERA is a flat partnership. Every engagement is led by a principal, and every line of work is done by a senior engineer — there are no juniors to hand your project to.
What we cover, together, is the full chain: ASIC and DSP design, SoC architecture, wireless PHY, embedded Linux and Yocto BSP, platform security and Common Criteria / FIPS certification. Very few consultancies can take a chip from RTL sign-off through secure firmware to a defensible Security Target. We can, because each of those disciplines is someone’s day job.
A lot of what we know is in public — in peer-reviewed conference and journal papers, granted patents, standards-body drafts, and upstream contributions to open EDA and simulation projects. Named references to specific work are shared under NDA.
The shape of a typical engagement: someone messages us with a block, a BSP, or a cert deadline that has to ship next quarter. We spend a week scoping the architecture, picking the toolchain, and writing the spec everyone can defend. The next four to sixteen weeks one of us is in your repo, opening pull requests, running regressions, and handing back soft IP, a hardened image, or an evaluation pack that your team can keep maintaining after we’re gone.
What each of us owns.
Every engagement is led by a principal, and every line of work is done by a senior engineer. Names are exchanged under NDA before a project starts — here are the roles and credentials that sit behind the work.
- Principal · 01 Netherlands
ASIC, DSP & functional safety
Fixed-point DSP and digital ASIC design, with years inside automotive and consumer semiconductor design houses. Maintains an open-source fixed-point arithmetic package for GNU Octave and several published DSP cores.
- // credentials
- PhD-level electrical engineering · ISO 26262 Functional Safety Practitioner · GNU Octave package maintainer · OpenCores contributor
- Principal · 02 Netherlands
Embedded Linux, cryptography & certification
Defense-grade embedded Linux and platform security, from Yocto BSP through post-quantum cryptography through Common Criteria Security Target authoring. Integrated Kyber (FIPS 203) into production WPA3 and authored Security Target evidence for NdCPP evaluation.
- // credentials
- MSc-level computer science · IEEE / IETF standards contributor · Common Criteria Security Target authoring · FIPS 140-3 / STIG track record · industry recognition awards
- Principal · 03 Netherlands
Wireless PHY & DSP algorithm design
Receiver and demodulator architecture across BLE, Bluetooth classic, 802.15.4, and UHF RFID. Design and verification of digital filters, FEC (Viterbi, Reed-Solomon, convolutional), and equalizers against real channel and RF-impairment models.
- // credentials
- PhD-level electronics & communications · peer-reviewed publications (double digits) · multiple granted patents · IEEE journal reviewer and conference TPC member
- Principal · 04 Netherlands
SoC architecture & NPU/AI acceleration
System-level SoC architecture, NPU and matrix-accelerator design, virtual prototyping (SystemC), and HW/SW co-design. Research background in hard real-time scheduling; upstream contributions to the Accellera SystemC reference implementation; HW acceleration deployed into semiconductor lithography tooling.
- // credentials
- PhD-level computer science · MSc with honours · IEEE Senior Member · HiPEAC Paper Award · ACM SIGBED recognition · Accellera SystemC contributor · peer-reviewed publications at DAC, DATE, EMSOFT
A public paper trail.
Every line below links to its source where available. None of it is on our word alone.
- // EU research university
PhD-level electrical engineering
Doctoral research in digital signal processing & integrated circuits
- // EU research university
PhD-level computer science
Doctoral research in hard real-time scheduling & system-level design
- // EU research university
PhD-level electronics & communications
Doctoral research in wireless PHY and RFID receiver algorithms
- // exida
ISO 26262 Functional Safety Practitioner
Automotive functional safety — FSP certified
- // Institute of Electrical and Electronics Engineers
IEEE Senior Member
Elevated grade — awarded for significant contributions to the field
- // GNU Octave community
Open-source package maintainer
Maintainer of an official fixed-point arithmetic package for signal-processing modelling
- // Accellera Systems Initiative
Accellera SystemC contributor
Upstream contributions to the SystemC reference implementation
- // European network on HPC & embedded architecture
HiPEAC Paper Award
Peer-reviewed award for research published at DAC
- // DSP, processor, and filter building blocks
Open IP core contributor
Synthesisable open cores released to the silicon community
How we work.
Verify first.
No RTL, BSP, or cryptographic integration ships without a self-checking verification. Coverage closure and evidence packs are the deliverable, not a bonus.
Tools serve the design.
Open source where it makes sense; commercial where it must. The flow exists to let you iterate, not to lock you in.
Document like the next engineer is you.
Every deliverable ships with a README, a Makefile, and a one-page architecture note. Every Security Target ships with assurance evidence.
What we bring on day one.
- SystemVerilog
- Verilog
- VHDL
- SystemC
- Matlab / Octave
- SVA
- Formal (SymbiYosys, JasperGold)
- UVM
- Hybrid RTL/SystemC DV
- Synopsys DC
- Cadence Genus
- Yosys + OpenROAD
- STA / sign-off
- Yocto · Buildroot
- OP-TEE · TPM · HSM
- OpenSSL + liboqs (PQC)
- Secure boot · FDE · MACsec
- Matlab / Octave + fxp
- Bit-true / cycle-true models
- SystemC virtual prototypes
- Make · CMake · Bash · CI regressions
- Common Criteria / NdCPP
- FIPS 140-3
- STIG
- ISO 26262
- IEEE / IETF